1. Field of the Invention
The present invention relates to a memory test circuit and method, and more particularly to a test circuit and method capable of detecting a defective portion of a memory.
2. Description of Related Art
In keeping with recent large-scale system LSIs, there is a tendency to increase a capacity of an internal memory. The cells of internal memory become multi-bit. In addition, the number of internal memories has increased. As a method of testing the memories, in general, BIST (built-in self-test) has been used. The BIST enables self-testing in a LSI by incorporating a test pattern generating circuit generating test patterns supplied to a circuit to be tested and a comparator circuit comparing data read from the circuit to be tested with expected value data. According to the BIST, a test pattern generating circuit and an expected value comparator circuit in the LSI are used to generate a memory test pattern in the LSI to test a target memory to output only pass/fail information.
However, what is obtained with a general test method based on BIST is only information about whether or not a failure occurs in the memory. A failure portion of the memory cannot be determined based on this information. For improving memory quality, it is necessary to determine a failure portion and analyze the failure to feed the cause of the failure back to a memory manufacturing process. To that end, there has been required a technique for obtaining information about a failure portion necessary for analyzing a failure of the memory.
Japanese Unexamined Patent Publication No. 2004-86996 (Hirai) discloses a technique of detecting a failure portion upon memory test. FIG. 1 is a block diagram of a memory test circuit of the Related Art 1 disclosed by Hirai. Referring to FIG. 1, the Related Art 1 is described below.
The memory test circuit of FIG. 1 includes a test memory controller circuit 101, a write data generating circuit 102, a memory 103, an expected value generating circuit 104, an expected value comparator circuit 105, a compare register 106, a test item detecting circuit 107, an address register 108, a fail bit detecting circuit 109, an FBM (fail bit map) memory control circuit 110, and an FBM memory 111.
The test memory controller circuit 101 executes write control and read control for testing the memory 103. The write data generating circuit 102 generates data to be written to the memory 103 upon memory test. The memory 103 is a memory to be tested. The expected value generating circuit 104 generates an expected value as a reference that would match with an output data value that is sent from the memory 103 during normal operations upon the memory test. The expected value comparator circuit 105 compares the reference expected value with the output data value from the memory 103. The compare register 106 holds comparison results for all bits, which are sent from the expected value comparator circuit 105. The test item detecting circuit 107 detects a test item number assigned to each of test patterns of the executed memory test. The address register 108 holds an address of a memory cell that sent out an output data value that is being compared by the expected value comparator circuit 105. The fail bit detecting circuit 109 detects a bit the comparison result of which shows that the expected value does not match the output data value, out of all bits held in the compare register 106. The FBM memory controller circuit 110 controls writing to the FBM memory 111 to which failure information is written. The FBM memory 111 stores values output from the test item detecting circuit 107, the address register 108, and the fail bit detecting circuit 109 as failure information.
A memory test mode signal TESTMOD and a test start signal MEMRST supplied from the outside of the LSI are input to the test memory controller circuit 101. A read address signal RADR output from the test memory controller circuit 101 is input to the expected value generating circuit 104 and the address register 108. A read control signal RE output from the test memory controller circuit 101 is input to the expected value generating circuit 104 and the test item detecting circuit 107.
Further, the test start signal MEMRST is also input to the write data generating circuit 102 and the FBM memory controller circuit 110. The write data generating circuit 102 outputs write data WDATA to the memory 103. The write data WDATA is input to the memory 103. Further, the test memory controller circuit 101 outputs a write address signal WADR, a write control signal WE, a read address signal RADR, and a read control signal RE. There signals are input to the memory 103.
Read data RDATA output from the memory 103 and expected value data EXDATA output from the expected value generating circuit 104 are input to the expected value comparator circuit 105. A pass/fail determining signal PASSNG is output from the expected value comparator circuit 105 to the outside of the LSI. Further, comparison data COMPDATA output from the expected value comparator circuit 105 is input to the compare register 106. Comparison result data COMPDATA 2 output from the compare register 106 is input to the fail bit detecting circuit 109. Further, a test suspending signal COMPPNG output from the expected value comparator circuit 105 is input to the test memory controller circuit 101 and the FBM memory controller circuit 110.
A memory analysis mode signal DEBGMOD and an analysis result read signal DEBGREAD supplied from the outside of the LSI are input to the FBM memory controller circuit 110. The FBM memory controller circuit 110 outputs an FBM address signal FBMADR, an FBM write control signal FBMWE, and an FBM read control signal FBMRE to the FBM memory 111.
The FBM memory 111 writes three signals, a test item data signal TESTNO output from the test item detecting circuit 107, an address data signal FAILADR output from the address register 108, and a fail bit signal FAILBIT output from the fail bit detecting circuit 109 as one data signal FBMDATA.
Here, the memory 103 has, for example, 256 addresses and stores 8-bit data. The data FBMDATA written to the FBM memory 111 is, for example, 14-bit data, and upper 3 bits correspond to the output signal TESTNO of the test item detecting circuit 107, subsequent 8 bits correspond to the output signal FAILADR of the address register 108, and the remaining 3 bits correspond to the output signal FAILBIT of the fail bit detecting circuit 109.
If a memory cell capable of storing data of 14 or more bits is used as the FBM memory 111, the failure information can be stored at a time. A capacity of the FBM memory 111 is determined based on the bit width of the memory 103 to be tested and the number of stored failure information. A signal output from the FBM memory 111 becomes an FBM read-out signal FBMOUT to be output from the LSI.
Operations of the memory test circuit of FIG. 1 are described next. A memory test mode signal TESTMOD supplied from the outside of the LSI sets a memory test mode. The test start signal MEMRST is input to thereby reset the test memory controller circuit 101, the write data generating circuit 102, and the FBM memory controller circuit 110. Further, the write data generating circuit 102 starts generating the write data WDATA.
Subsequently, the test memory controller circuit 101 generates a write address signal WADR and a write control signal WE to be written to a memory cell. Further, the write data WDATA is written to the memory 103. If data is written to all addresses, the write address signal WADR and the write control signal WE are stopped.
Next, the test memory controller circuit 101 generates the read control signal RE and the read address signal RADR. Further, the expected value generating circuit 104 generates expected value data EXDATA corresponding to the read address signal RADR.
The expected value data EXDATA generated with the expected value generating circuit 104 is compared with the read data RDATA read from the memory cell by the expected value comparator circuit 105. Based on the comparison result, the expected value comparator circuit 105 outputs a high-level signal if read data of all bits match with the expected data. If the read data for only 1 bit does not match the expected value, a low-level signal is output as the pass/fail determining signal PASSNG. Further, the read address signal RADR is stored in the address register 108 unless a comparison result corresponding to an address value is obtained. Further, the test item detecting circuit 107 counts read control signals RE to detect a test item number TESTNO representing a position of a sub-test pattern in the test pattern. The test item number TESTNO is information for determining which test item of the test pattern a failure occurs in. A test pattern of this time can be known based on the test item number TESTNO.
Further, provided that the memory analysis mode signal DEBGMOD supplied from the outside of the LSI is a high-level one, and an operational mode is a memory analysis mode, if a comparison result of the expected value comparator circuit 105 is negative, the test suspending signal COMPPNG is switched to a high level during a period corresponding to fail bits. Reading the next address is stopped in the test memory controller circuit 101 only during a period one clock shorter than a period where the test suspending signal COMPPNG is at high level. That is, if a failure is found for one 1 bit, the operation is not stopped. If a failure is found for 3 bits, the operation is stopped for a period corresponding to 2 clocks.
Further, the comparison data COMPDATA for all bits that are sent from the expected value comparator circuit 105 are held in the compare register 106, and the fail bit detecting circuit 109 detects an unmatched bit value. The test item number, the failure address, and the failure bit are concurrently written to the FBM memory 111 as one failure information. If only a failure of 1 bit is found at 1 address, the data needs only to be written once. If failures of plural bits are found, the fail bit detecting circuit 109 detects fail bits in order, and the data is written to the FBM memory 111 plural times. A FBM memory cell control circuit 110 counts FBM address signals FBMADR if the test suspending signal COMPPNG is a high-level one.
Further, after the completion of testing, if the analysis result read signal DEBAGREAD is at high level, the FBM memory controller circuit 110 enters a read mode, and failure information is read from the FBM memory 111 and output as the FBM read-out signal FBMOUT.
Meanwhile, Japanese Unexamined Patent Publication No. 2002-32998 (Suzuki) discloses another technique of detecting a failure portion upon memory test. FIG. 2 is a block diagram of a memory test circuit of the Related Art 2 disclosed by Suzuki. Referring to FIG. 2, the memory test circuit of the Related Art 2 is described below.
The memory test circuit of the Related Art 2 as shown in FIG. 2 includes a memory 201, a memory BIST circuit 202, and a logic scan chain circuit 203. Further, the memory BIST circuit 202 includes an address counter circuit 2021, a data generating circuit 2022, a comparator circuit 2023, and a BIST controller circuit 2024. The logic scan chain circuit 203 includes plural scan register groups 203-1 to 203-n.
The memory 201 is a memory to be tested. An address counter circuit 2021 generates an address for testing the memory 201. The data generating circuit 2022 generates an expected value as a reference which would match with an output data value sent from a memory under normal operations upon the memory test. The comparator circuit 2023 compares the reference expected value generated with the data generating circuit 2022 with an output data value from the memory 201. The BIST controller circuit 2024 controls the address counter circuit 2021, the data generating circuit 2022, and the comparator circuit 2023 for generating a memory test pattern.
The logic scan chain circuit 203 is used for a testing method called scan test that flip-flops (F/Fs) out of logic circuits except a memory are connected through a line 205 in a test mode to realize shift register configuration to thereby improve controllability and observability for testing the memory. The logic scan chain circuit 203 is divided into scan register groups 203-1, 203-2, . . . , 203-n in accordance with the number of F/Fs that can store failure information. The scan register groups 203-1, 203-2, . . . , 203-n are configured to shift data in a direction 204 from the scan register group 203-1 toward the scan register group 203-2.
Operations of the memory test circuit of the Related Art 2 are described next. If the memory BIST circuit 202 becomes active, the BIST controller circuit 2024 becomes active to start testing the memory 201. Upon the memory test, the logic scan chain circuit 203 shifts data in the direction 204 from the scan register group 203-1 to the scan register group 203-2.
The comparator circuit 2023 of the memory BIST circuit 202 compares an output data value from the memory 201 with an output expected value from the data generating circuit 2022. If a failure is detected as a result of comparison, an address value where the failure is detected and a data value representing the failure determination result output from the comparator circuit 2023 are input to the scan register group 203-1 as failure information. From then onward, the memory test is continued even after a failure is detected. If the next failure is found, the data stored in the scan register group 203-1 is shifted to the scan register group 203-2, and the found-failure information is input to the scan register group 203-1 this time. In this way, the failure information is captured by the logic scan chain circuit 203 while being shifted, thereby making it possible to capture up to n failure information. After the completion of the memory test, the failure information held in the logic scan chain circuit 203 is shifted and output to the outside from an SDO (Serial data out), making it possible to obtain the failure information.
In the Related Art 1, the FBM memory 111 stores, as failure information, a test item number, a failure address, and a fail bit. The test item number is determined such that the test item detecting circuit 107 counts read control signals RE to determine a position in the memory test pattern. The test item number is used for determining which test pattern a failure occurs in. However, a test pattern for testing the memory 103 is obtained by combining sub-test patterns ““0” is written as a data value to memory cells-in ascending order of addresses”, “data is read from the memory cells in descending order of addresses”, ““0” and “1” are alternately written to the memory cells in descending order of addresses”, ““0” and “1” are alternately read from the memory cells in ascending order of addresses”. Thus, the memory test circuit of the Related Art 1 includes only information about the number of read data in the memory test pattern. Therefore, unless compared with all sub-test patterns of the used memory test pattern, it cannot be determined how a memory under test is operating when a failure occurs. That is, there arises a problem in that, unless all sub-test patterns of the memory test pattern are grasped, a failure portion cannot be checked.
Further, in the Related Art 1, failure information is written to the FBM memory 111. However, there is another problem in that, if a memory large enough to store failure information cannot be prepared, failure information remains to be stored.
On the other hand, in the Related Art 2, a failure address and a fail bit are stored as failure information. However, there is a problem in that which test pattern is executed and where a sub-test pattern involving a failure is in the memory test pattern cannot be determined based oh the information about the address and fail bit alone.
Further, in the Related Art 2, the logic scan chain circuit 203 captures the failure information. However, similar to the Related Art 1, there is another problem in that failure information remains to be stored if exceeding a memory capacity.